Over the past decade, the bandwidth and data transmission rate required for computing applications have been increasing year by year. In major industries, bandwidth demand doubles approximately every three years. This is mainly driven by a compound annual growth rate of up to 45% for telecommunications services, cloud computing services, and information technology providers, particularly in the banking, securities, and insurance sectors. In addition, artificial intelligence (AI) companies based on Large Language Models (LLMs) are also continuing to expand their business. Industrial automation, including AI aided detection and autonomous vehicle, also promotes the need for higher bandwidth and faster data speeds.
The infrastructure that provides high-speed data for these applications includes wired and wireless networks. But in high-performance computing (HPC), high-speed testing equipment, and gaming hardware, the connection between the central processing unit and peripherals must also support continuously increasing data transfer rates.
The Power of PCIe
Networking devices or components connected to the central processing unit require a simplified way to quickly and accurately transmit data, which is peripheral component interconnect (PCI) technology. Various computing sub markets, including servers and data centers, automotive and industrial, workstations and handheld devices, adopt PCI Express (PCIe) point-to-point serial architecture to achieve fast and reliable data transmission.
PCI-SIG， It is the abbreviation for Peripheral Component Interdisciplinary Group, an alliance of approximately 900 member companies responsible for developing and managing open industry standards for PCIe technology (Figure 1).
PCIe specification data rate (Gb/s)
(Encoding) Unidirectional x16
Channel bandwidth * annual
1.0 2.5 (8b/10b) 32 Gb/s 2003
2.0 5.0 (8b/10b) 64 Gb/s 2007
3.0 8.0 (128b/130b) 126 Gb/s 2010
4.0 16.0 (128b/130b) 252 Gb/s 2017
5.0 32.0 (128b/130b) 504 Gb/s 2019
6.0 64.0 (PAM-4, Flit) 1024 Gb/s
(~1 Tb/s) 2021
*- Bandwidth after deducting encoding overhead
Figure 1: Since 2003, the PCI connection component specifications of PCI-SIG have been supporting the continuous growth of data transmission rates. (Image source: PCI-SIG)
The organization released the PCIe 1.0 standard in 2003, which supports 2.5 gigabits per second (GT/s) transmission and met the requirements of the 3G wireless standard at that time. The subsequent updates paved the way for the annual increase in I/O throughput while ensuring backward compatibility. For example, devices that meet the PCIe 5.0 specification can achieve a rate of 32.0 GT/s per channel, and are compatible with the 5G network required for streaming media and edge computing.
These higher throughput provide support for low latency required for AI and edge processing, industrial automation, testing equipment, and gaming. The point-to-point architecture of PCIe technology also supports high energy efficiency performance, which is a key consideration for advanced computing applications.
Maintain cooling of HPC components
Even with the improved data rates and energy efficiency provided by the latest PCIe technology, high-performance computing (HPC) applications such as real-time financial fraud detection, AI big language modeling systems, and computational fluid dynamics (CFD) still require multiple parallel processors. Managing heat dissipation and space constraints while meeting this demand is not an easy task, especially when there is competition for space between data cables and airflow channels connecting components and processors.
In this case, designers of high-performance computing devices will switch to using flat, foldable PCIe extension cable components, such as 3M's 8KDx series (Figure 2).
3M 8KDx Series PCIe 5.0 Extension Cable Component Image
Figure 2: 3M's 8KDx series PCIe 5.0 extension cable assembly is a flat flexible cable assembly that can fold itself. (Image source: 3M)
The 8KDx series is designed according to the PCIe 5.0 standard and is backward compatible with systems designed according to early PCIe standards. They come in two models, x8 and x16, with eight and sixteen wires respectively. Provide options for jumper installation and surface mount (SMT) terminals.
The 30 AWG silver plated wire is precisely placed within a continuous stack of shielding layers, with an overall thickness of 0.74 mm. The conductor pairs of traditional wires are longitudinally wrapped in a spiral shielding layer, while the 8KDx series extension wire is thinner and softer compared to it. A more flexible design allows multiple PCIe extension cords to be bundled and folded together without blocking critical airflow (Figure 3).
Picture of 30 AWG wire with continuous stacking and precise placement
Figure 3: The continuous stacking and precise placement of 30 AWG wires enable the 8KDx series to connect components without obstructing airflow. (Image source: 3M)
Synchronous high-speed testing equipment
High performance computing applications rely on parallel processing to handle large datasets, while high-speed testing equipment must be connected to other peripherals such as processors, signal generators, graphics cards, and oscilloscopes. These systems require synchronous signals and low latency to ensure the validity of test data.
PCIe 3.0、 The 4.0 and 5.0 standards support signal synchronization with a single clock or multiple clocks. Technologies manufactured according to these standards, such as the 8KDx series, rely on 128 b/130 b encoding. In this encoding protocol, the data packet contains 128 bits of information, bounded by the 2 bits that mark the beginning and end of the packet. The start and end bits are used for clock synchronization and error detection, thereby using the remaining bits in the data packet for data transmission.
The 8KDx series PCIe extension cable uses wires with an impedance of 87 ± 5 Ω to further ensure data speed and integrity. When connected to the baseline 85 Ω impedance of systems built according to PCIe 3.0, 4.0, and 5.0 standards, these conductors can minimize impedance mismatch and signal reflection to the greatest extent possible.
In addition, testing engineers can confidently utilize the flexibility and space saving design of the 8KDx series components. Tests have shown that compared to unfolded cables, signal integrity does not decrease when the cable folds itself (Figure 4).